D Flip Flop, JK Flipflop, T Flip Flop Toggling Conditions Race Around Condition Conditions to Overcome Racing Master Slave Configuration The behavior of Master-Slave Flip-Flop Preset and Clear inputs in Flip Flop State Table, State Diagram State Equations. excitation table
Types of Counters Ripple or Asynchronous Counter The subsequent flipflop gets the clock input from the previous output Synchronous Counter All the flipflops get separate clock Differences between Asynchronous Counter and Synchronous Counter. 3 Bit Asynchronous Up Counter Logic design (JK Flipflop) Clock Diagram 4 Bit Asynchronous Up Counter – T flipflop 3 Bit Asynchronous … Read more
Flip Flop is 1 Bit memory cell. To increase the storage capacity we have to use group of flip-flop. this group of ff is known as REGISTER. n bit register consist of n number of flip-flops. Data formats & Classification of Registers data can be entered in serial or in parallel form. Classification of Registers … Read more
Basic Gates: NOT, AND & OR Universal Gates: NAND & NOR Arithmetic Gates: X-OR & X-NOR NOT Gate symbol, equation, and truth table. AND Gate If any of the input is low then the output is low. Output is high (1) only when all the inputs are high, otherwise low (0) Symbol \(Equation : Y=a.b\) … Read more
Sets of rules to simplify the given logic Complement \(A\) complement \(= \overline{A}\) or \(A’\) \((A’)’ = A\) AND \(\begin{aligned} A.A&=A \\ A.0&=0 \\ A.1&=A \\ A.A’&=0 \end{aligned}\) OR \(\begin{aligned} A+A&=A \\ A+0&=A \\ A+1&=1 \\ A+A’&=1 \end{aligned}\) Distributive Law \(\begin{aligned} A.(B+C) &= A.B+A.C \\ A+(B.C) &= (A+B).(A+C) \end{aligned}\) from there, we can get \(\begin{aligned} … Read more